This disclosure relates in general to engineering design automation (EDA) tools and, but not by way of limitation, to printed circuit board (PCB) tools that facilitate co-design of the package, integrated circuit (IC) and/or PCB.
PCB layout is a process prone to error. Interfaces and custom packages require hand-layout that are susceptible to human error. The exchange of signal names and pin assignments between different PCB and package layout tools is often done with a flat netlist or spreadsheet file. By far, the most prevalent approach to exchanging interface information today is using a spreadsheet to show the logical to physical assignments. For a connector that is 4×40 pins spreadsheet would be used to model this as 4 rows and 40 columns. The name of the signal would be entered into each column and the cell numbering would be used for the corresponding pin assignment. For a ball-grid array or bump pattern on a die the same approach is taken but the matrix is often much larger. The output of spreadsheet or other basic text file that can be imported into a connectivity tool, schematic in many situations, to create the electrical connectivity with actual pin assignments. This manual solution relies on the use of a signal name that is consistent across all tools and domains that are being operated upon.
When PCB layout and editing is done, it is pin-by-pin and wire-by-wire. Any naming conventions must be properly followed or connections between package and die or between connectors will route incorrectly. Each wire is connected individually or from a flat netlist, which has no appreciation of how signals are grouped. Simple naming errors get propagated through the design and requires extensive manual verification and possibly work-arounds should any errors not be found early in the process.
Tools for PCB layout often have a library of defined parts. In each library component, the corresponding package is defined on a pin-by-pin basis. Wires can be added to connect pins from the various packages. The wires can be read from a flat netlist, but there is not the ability to group similar signals or move them around on custom packages during the design process. With custom packages and new parts being common, libraries are inevitably out of date. When working with a package in the PCB layout all the pins are flattened as there is no grouping. Finding simple errors is difficult as designs get larger and more complex.
Conventional systems have difficulty when interfacing to different components with suites of different EDA tools. Keeping track of board signals with connectors, custom packages and co-design packages uses manual naming. Between tools, assigned signal names must correlate to provide proper connectivity between these interfaces. Signal connections to a pair of connectors that are used to join two boards, either via a connector to connector mating or using a cable, should be simple, but in practice are prone to introducing errors. Also, the signal to bump (die connection) and signal to ball (IC package connection) are difficult to coordinate so that the electrical and physical constraints in each domain are met. Without an optimal assignment in these domains the physical routing resources become cost prohibitive. Managing the tradeoffs between domains and ensuring that the electrical and physical requirements are difficult to manage.